Realization of Reading-based Ternary Łukasiewicz Logic using Memristive Devices

Memristive devices can not only be used as nonvolatile memories but also enable computation-in-memory (CIM) computing paradigms. CIM architectures show prospects in significantly reducing the data interaction time and energy consumption between processors and storage, thus addressing the bottleneck problem of the von Neumann architecture. Additionally, the capability of memristive devices to store multiple (resistance) states in one cell offer vast potential for CIM’s multi-valued logic, as they greatly enhance data storage density and computational efficiency. In this study, a novel concept for ternary Łukasiewicz logic utilizing the voltage divider of two (anti-)serially connected memristive devices is proposed. As this approach does not require any switching in the computation process and features a straightforward circuit architecture, a low energy consumption per operation is achieved. In addition, the concept is crossbar-array compatible. The concept is validated by circuit simulations using the JART VCM v1b model that has been calibrated to experimental data of a Pt/Ta
2
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/W memristive device.