Proposal & Investigation of Schottky Ring Engineered Reconfigurable Nanowire Transistor

This work presents a junction-engineered Schottky Ring Engineered Reconfigurable Nanowire Transistor (SR
²
NT) with a dual gate for the first time. Schottky Ring (SR) is present on either end of the Silicon Nanowires, resulting in an improved current for the device. This is because of an increase in the cross-section area for tunneling. The proposed device exhibits a very high I
ON
/I
OFF
ratio ~ 10
¹⁰
(ION ~ 10
^-6
and IOFF ~ 10
^-16
A) with relatively small threshold voltages (VTH) of 0.72 (-0.75) volts as compared to previously reported experimental data of 10
⁷
and 2 (1.8) volts for n (p-FET) device respectively. This is owing to the presence of high-κ material as gate dielectric; hence, there will be an increase in the barrier tunneling. A Maximum Current Density of 1618 (884) kA cm-2 for n-FET (p-FET) is also reported at 50% scaled supply voltage. An improvement in the Subthreshold Slope (SS) of 56% (53%) and 51% (30%) is obtained as compared to the experimental dual gate and triple gate Nanowire transistors, respectively. The benchmarking results confirm that the SR
²
NT is a strong contender for future Nanoscale devices.