Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms

In large-scale designs, the multi-FPGA system is a popular approach for hardware acceleration and pre-silicon verification due to its scalable capabilities. Researchers aim to enhance communication bandwidth and decrease latency between FPGAs, all while working within the constraints of limited physical pins available. To address this issue, we propose an optimization for time-division multiplexing(TDM). This optimization combines the advantages of traditional logic multiplexer circuits and high-speed serial circuits by utilizing the serial-to-parallel converter (ISERDES) and parallel-to-serial converter (OSERDES). The I/OSERDES approach typically employs the low-voltage differential signaling standard (LVDS) for high-speed data transmission, necessitating two physical pins. To save one physical pin, we advocate for a single-ended transmission solution without a forward clock. Moreover, we propose a new algorithm at the receiver to align the phase of the receiver’s clock. In comparison to the LVDS-based solution, our proposed interface achieves double the communication bandwidth of inter-FPGA chips without introducing additional system latency under the same TDM rate.