A 70dB SNDR 20MHz-BW VCO-Based CT Sturdy MASH Delta-Sigma Modulator with Robust Quantization Error Extraction

This paper presents a continuous-time (CT) Sturdy multistage noise-shaping (SMASH) Delta-sigma Modulator (DSM), proposing a quantization noise extraction scheme without traditional analog delay matching circuits, improving modulator’s robustness and relaxing performance requirement for building blocks. For power-efficiency, the first-stage’s quantizer is designed with a 5-bit Voltage Controlled Oscillator (VCO) based analog-to-digital converter (ADC) and the second-stage’s quantizer is implemented by a 5-bit first-order noise-shaping (NS) successive approximation register (SAR) ADC. A transistor-level prototype is implemented in 40nm CMOS and the simulation results show that the modulator’s SFDR and SNDR is 85.8dB and 70.4dB respectively over a bandwidth (BW) of 20MHz while consuming 7.13mW, leading to an excellent FoM of 164.9dB.