An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting

High-resolution Discrete-Time ADCs are challenging to drive due to their large input sampling capacitance for thermal noise suppression. Predictive level-shifting, an integrated input driving technique for high-resolution ADCs, enables rail-to-rail linear operation of the input buffer without requiring a higher supply voltage. Using this technique, a predictor implemented as an active analog differentiator is used to preset an analog level shifter so that the input signal is shifted toward the smaller range. In this paper, a digital predictor based on a finite impulse response (FIR) filter is explored to overcome the limitations of the analog predictor, such as process, voltage and temperature (PVT) variations and device saturation. The digital predictor saves 48% power and produces 58% less prediction error compared to its analog counterpart, resulting in a more power-efficient ADC system.