An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR

This paper presents an 11-bit 12GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30fs step-size. The ADC achieves a voltage gain of 8.55dB in steering direction. An overall SFDR and SNDR above 68dBc and 55dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.