Neural Network Acceleration Using Digit-Plane Computation with Early Termination

Deep neural network (DNN) hardware accelerator designs can be divided into two categories, bit-parallel and bit-serial, depending on whether the input of the multiplication is in bit-parallel or bit-serial style. Bit-serial DNN designs with only shift-add operations are more flexible for computation when the per-layer bit-widths are different in aggressive model quantization. Rectified Linear Unit (ReLU) is a common non-linear activation function after each layer of DNN computation where negative values are replaced by zeros. Thus, early-termination could be employed to reduce ineffective computation, resulting in improved speed performance and reduced energy consumption. In this paper, we propose a new bit-serial computation style by re-organizing data in bit-plane order. We observe that bit-plane computation allows more efficient early-termination. The proposed bit-plane DNN design is also extended to digit-plane through radix-4 Booth recoding, leading to a smaller area cost. Experimental results show that the speed performance of the proposed designs is 2.25x and 1.48x times that of the bit-parallel and bit-serial designs respectively when executing the VGG-16 model.