POCO: Hardware Characterization of Activation Functions using POSIT-CORDIC Architecture

POSIT offers a wider dynamic range when compared to floating-point (FP) formats with lesser number of bits. Such data formats are required to address the need for low-bit high-precision hardware architectures for neural networks (NNs) on edge platforms. Activation functions (Af) which introduce non-linearity during the feature extraction process remain as a core component for realizing NN systems. CORDIC (COordinate Rotation Digital Computer) architecture is a hardware efficient technique to realize complex non-linear functions and is deemed suitable to implement Afs. Hence, this work aims to investigate POSIT data formatted CORDIC architecture to realize Afs (Tanh, Sigmoid and Softmax) in different architectural styles. A benchmark evaluation for the proposed POSIT data formatted Afs with the improved CORDIC architecture over SOTA (IEEE 754 FP formats) based designs are presented. The noticeable improvement in hardware design space and error metrics makes the CORDIC architecture-based POSIT formatted Afs stand out over other methods. All the design files are made publicly available for easy adoption and further usage to the designers’ and researchers’ community.