A Constant-Quiescent-Current and Fast-Transient CL-LDO with 99.99% Efficiency Using Dynamic Embedded Slew-Rate Enhancement Circuit

This paper presents a low constant quiescent current and fast transient response capacitor-less low dropout regulator (CL-LDO) with high current efficiency, achieved using a dynamic slew-rate enhancement (SRE) circuit. The proposed CL-LDO achieves a fast transient response without requiring additional current under heavy loads, enabling a peak current efficiency of 99.99%. Designed using a 55-nm standard CMOS process, the CL-LDO consumes a quiescent current of 10 µA. It can deliver 0.2-100 mA of load current at a 1.0-V output from a 1.2-V to 1.5-V supply voltage. Additionally, it achieves a settling time of 0.418 µs and an overshoot/undershoot voltage of 74 mV/166 mV for load steps ranging from 0.2 mA to 100 mA, with an edge time of 0.1 µs.