A Low Power Analogue Compressed Sensing Approach for CMOS ISFET Arrays

In this work, we propose a novel approach to integrate a scalable compressed sensing methodology in the analogue domain with a CMOS ISFET array. A current conveyor is employed with a switched capacitor to encode the output current from each ISFET sensor to a corresponding charge onto a capacitor, following by a pseudo-random non-zero diagonal sampling matrix that is generated by Linear Feedback Shift Registers (LSFR) for array sampling. The design also features a 12-bit Successive Approximation Register (SAR) ADC, enabling power efficient conversions at 50 KSamples/s using a 1.25 MHz clock, with an ENOB of 10.3. The 32 × 32 array is divided into 16 clusters, each containing 64 pixels arranged in an 8 × 8 configuration serving as a compressed sensing unit block. The overall system is designed under a 65 nm process occupying a silicon area of 0.375 mm
²
. It operates at a programmable frame rate of 30 - 240 fps, with an overall power consumption of 17.13 -117.23 μW, and a lowest energy per pixel of 394 pJ in compressed sensing mode. We verify the performance of the system with a PSNR comparison for image quality under two scenarios where CS is either enabled or disabled.