Design of CNFET-based Ternary Conditional Sum Adders using Binary Carry Propagation

This paper presents a new methodology to implement ternary Conditional Sum Adders (CSA) using CNFETs. The existing design of ternary conditional sum adders conditionally compute sums corresponding to three possible carries 0, 1 and 2, and use 3:1 multiplexers for correct carry and sum selection. This technique results in a complex carry propagation path. In this work, we present a new approach, which transforms the possible carries from {0,1,2} to {0,1}. This transformation enables the use of a 2:1 multiplexers for conditional selection of sum and carry signals, for only two possible carry values similar to binary CSA. The existing and proposed CNFET-based ternary CSAs are implemented using HSPICE. Simulation results show that the proposed ternary CSA results in up to 87% reduction in average power consumption, 27% reduction in propagation delay, and 90% reduction in Power-Delay Product when compared to CNFET-based ternary CSAs existing in the literature.