An Optimized Architecture for Computing the Square Root of Complex Numbers

In this paper, we propose an optimized architecture for computing the square root of complex numbers based on the piecewise linear (PWL) method. In the proposed design, the square-add and multiply-add operations are the focus of optimization. The symmetry of the partial products of the square operation is used to reduce the number of partial products. In addition, the least significant bits (LSBs) of the square-add and multiply-add are truncated to reduce the bits of partial products. According to the optimization of the hardware circuit, the simulation of the circuit in the segmentor is modified by introducing the simulation of the truncated fused square-add operation and truncated fused multiply-add operation. Experimental results show that the proposed optimization architecture has superiority in area, delay and power when compared with state-of-the-art designs.