A Write System for Compact RRAM Memory Arrays Based on F-1T1R

This paper presents a novel write system for memory array with RRAM devices. Our design targets the minimization of the write circuit area and a more compact memory array, by avoiding large-area IO transistors and exploiting the back-gate control in FD-SOI technologies. Indeed, thanks to the Flipped (F)-1T1R cell, replacing the standard 1T1R for the data storage, read and write peripheral circuits, on the columns, can be designed with core devices, to withstand the low reset voltage, for a reduced column pitch. Designed in a 22-nm FD-SOI technology, without IO devices, our write system can safely provide a forming voltage above 3 V and a reset voltage of 1.35 V, with very low values of leakage current. From the optimized layout, we obtained an area ratio, between the write system and the full memory, below 10%, for a memory array with 400 rows and columns.