A 4th Order CIFB High Dynamic Range Sigma-Delta Modulator with Multi-level Quantizer and Intrinsically Linear Capacitive DACs

The linearity of the digital-to-analog converter (DAC) is a key bottleneck for high-resolution Sigma-Delta modulators that use multi-level quantizers. To address the DAC non-linearities caused by element mismatches and achieve a high signal-to-noise-and-distortion ratio (SNDR), this work exploits intrinsically linear capacitive DACs to improve the design of a high-resolution Sigma-Delta modulator with 4
^th
-order, discrete-time architecture realized as a Cascade of Integrators with Feed Back (CIFB), and 3-level/5-level quantizers. The error due to capacitive element mismatch is mitigated by using an extra reference voltage and reconfiguring DAC topologies so that distortions brought by capacitor mismatches are largely reduced. We demonstrate in simulation results that a 128.9 dB modulator SNDR can be obtained in the presence of up to 1% DAC capacitance mismatch combined with 2% reference voltage variation, achieving 60 dB SNDR improvement compared with a design with a conventional DAC structure.