On-chip Data Compression Techniques for High-Density Implantable Neural Recording

Brain-machine interface (BMI) devices have emerged as a promising solution for a wide range of neural disorders ranging from depression, epilepsy, and Parkinson’s disease. Implantable neural recording circuits to realize BMI devices mostly rely on off-chip computation either to train a classifier or train and infer off-chip. This results in the need for efficient off-chip data transmission with constrained power budgets. This work delves into on-chip compression of neural signals for energy-efficient data transmission. We provide a comparative study of two hardware-efficient algorithms: Compressed Hadamard Transform (CHT) and Compressed Sensing (CS), in the context of high-density neural data compression. The CHT and CS compression engines along with the data interface and stimulator digital core were implemented on a 65nm CMOS technology and compared for their area, power, and reconstruction error performance. We conclude that the CHT approach is 6.6% power and 6.5% more area efficient while still providing better reconstruction compared to CS technique.