AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks

Neuromorphic Computing presents a resource-efficient computing paradigm by enabling brain-inspired low-power computations. This compute efficiency can be attributed in large part to the nature of analog computations and bio-inspired spiking data. However, the hardware implementation of a general-purpose or reconfigurable SRNN for neuromorphic computations poses challenges, especially pertaining to the programmable connectivity between neurons. This challenge becomes more pronounced when dealing with analog spikes, where information is encoded in the timing, width, shape, and frequency components of the spikes. Existing approaches to reconfigurable spike routing Network-on-Chip (NoC) architectures are predominantly packet-based, falling short when preserving the majority of information within the spike. This becomes especially problematic for small-scale SRNNs, where these packet-based approaches lead to information loss while introducing unnecessary overhead, leading to increased power consumption and NoC implementation area on-chip. To address this challenge, this work introduces AnSpiCS-Net: Analog Spike routing Circuit Switched Network-on-Chip. AnSpiCS-Net utilizes a circuit-switching-based architecture with a Clos network topology, employing three distinct switch types: transmission gates, NMOS, and PMOS switches. The NMOS switch-based configuration achieves a balanced performance across various design metrics, while the transmission gate configuration excels in spike signal integrity. Various implementations of AnSpiCS-Net are assessed based on critical implementation metrics, including latency, throughput, power consumption, and area. AnSpiCS-Net proves highly efficient, offering nearly a 48x reduction in area for the transmission gate-based configuration compared to packetized NoC architectures in existing literature.