A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces

This paper presents a single-ended hybrid digital-to-analog converter (DAC)-based transmitter (TX) using four-level pulse-amplitude modulation (PAM-4) for memory interfaces. The proposed hybrid DAC composed of voltage mode (VM) driver unit segments and current mode (CM) driver unit segments reduces the total number of unit segments without increasing complexity in impedance matching. Therefore, the hybrid DAC significantly reduces area and the associated power consumption. Digital signal processing (DSP)-based feed-forward equalization (FFE) provides precise and flexible equalization. The proposed linearity enhancement technique compensates for additional non-linearity caused by short-length devices in the CM driver segments. The proposed TX operating at 40Gb/s/pin consumes 30.9mW with 1.0/0.9/0.15V supply voltages, achieving 0.77pJ/bit energy efficiency and a level separation mismatch ratio (RLM) of 0.989. The TX occupies an active area of 0.023mm
²
.