Hardware Acceleration of Phase and Gain Control for Analog Beamforming

The beamforming technique has been widely used to improve the link budget in wireless communications. Compared with the digital beamformer, the analog beamformer has much lower hardware complexity and is more suitable for low-cost mobile applications. In this paper, we consider element-level phase and gain control of the analog beamformer using two phase shifters only. By setting the phase shifts properly, simultaneous 360
^◦
phase and 6-dB gain control (SPGC) can be achieved to form the beam pattern. We first propose a low-complexity SPGC method tailored for massive multiple-input multiple-output (MIMO). Based on the conventional and proposed SPGC methods, we then design the full-featured accelerator (FFA) and the hardware-efficient accelerator (HEA) to accelerate the computing process. These two accelerators are implemented in 28 nm technology. FFA integrates 137 kilogate equivalents (kGE) in a core area of 0.0693 mm
²
and dissipates 104.4 mw at 2.0 GHz with 16 degrees of parallelism, while HEA can reduce the core area by 44.6% and power consumption by 42.7% without significant performance loss.