The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory

Bias temperature instability (BTI) has posed increasingly long-term reliability issues in modern static random access memory (SRAM) applications, especially for configuration memory in FPGA. In this work, we present an aging-aware 8T SRAM design for the implementation of FPGA configuration memory. First, we adopt a body-source short scheme to bias the p-body at VDD/2, which effectively mitigates the negative BTI for PMOS. Second, we bias the leaking transistors in the supercutoff region with an optimized dynamic leakage-suppression logic, which helps to reduce the leakage power (thus lower temperature) and further mitigate the impact of BTI. Third, we achieve an operating voltage range from 0.9V to 0.6V of the 8T SRAM, which benefits the optimization of lifetimes and leakage power in the idle mode (0.6V). Compared with the state-of-the-art, post-layout results with the TSMC 28nm aging model show that our 8T SRAM-based FPGA achieves the highest figure of merit (FoM) for lifetimes with a 2.33× extension. Moreover, it further achieves a 65.2% reduction in leakage power in the idle mode.