A Low Power Programmable Switch Supply Dynamic Comparator

This paper introduces a programmable switch supply comparator that uses a programmable reservoir capacitor to achieve a reduced effective supply voltage during the decision phase. This comparator achieves up to 50% power consumption reduction against the conventional dynamic comparator. Fabricated in 65nm CMOS, the silicon results of the PMOS-input programmable comparator show programmable power consumption and energy efficiency ranging from 2.7 - 4.1μW and 0.22 - 0.5pJ/conv, respectively. Similarly, the input-referred noise can be programmed from 100 - 180μVrms. Additionally, the power (energy efficiency) and input-referred noise can be programmed at any clock cycle, making this design an ideal solution for the two-comparator SAR ADC architecture.