Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects

Hardware Trojans and side-channel attacks pose significant threats such as sensitive information leaking and/or malfunctioning to modern cryptoprocessors. To overcome those threats, Physical Unclonable Function (PUF) has been considered one of the security primitives for secret keys or unique IDs due to the characteristic of stable, random, and unique responses. However, most existing PUF designs, which operate independently of the original circuit, are vulnerable to removal attacks and result in substantial resource overhead. To address these issues, authors in [5] proposed parallel scan-chain PUF, which is built on the standard Design-for-Testability (DFT) structure of scan flip-flops. However, aging effects, such as Bias Temperature Instability (BTI) and Hot Carriers Injection (HCI), significantly impact input conditions between two Scan Flip-Flops (SFFs) in normal mode, leading to complex Error Correction Codes (ECC) and increased area overhead. Therefore, we introduce a novel design to mitigate aging effects, enhance reliability, and analyze the parallel scan-chain PUF structure to identify error causes. Besides, to decrease the errors caused by aging effects, we use the proposed aging compensator to offset the delay between two different SFFs after aging mutually. Additionally, we incorporate signal gating for the arbiter, mitigating unbalanced aging effects and saving power consumption. Experimental results demonstrate that the proposed method can reduce the responses from an average error rate of 39.96% to less than 7.5% within 10 years. Moreover, with the complexity of ECC reduced, it offers ~8x overhead reduction for the Bose–Chaudhuri–Hocquenghem (BCH) encoder and decoder.