A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching

Flip-flops with ultra-wide-range dynamic voltage scaling capability are attractive for ultra-low power applications. In this paper, a single-phase split-controlled flip-flop (SCFF) is proposed for ultra-wide-range dynamic voltage scaling. By employing a differential structure in the master latch and a unique split-controlled slave latch, the proposed SCFF possesses desirable features for ultra-low voltage operations. Designed in a 55-nm low-power CMOS technology, SCFF achieves 0.4 V minimum supply voltage, and reduces the power-delay-product (PDP) by up to 79.7% compared to the state-of-the-art flip-flops at the typical process corner with 12.5% input toggle rate. SCFF also maintains the benefit of low PDP at different process corners and different supply voltages.