Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics

In the evolving technological landscape, the pursuit of high-performance systems is paramount. Achieving a balance between Power, Performance and Area (PPA) – the core elements of chip design – becomes increasingly daunting in light of mounting technological intricacies. To address this challenge, this paper introduces the Nested Flex technique, specifically devised to construct resilient clock networks in non-uniform channel partitions by maximizing the shared path in the clock network. This approach elevates clock quality in comparison to conventional clock tree networks. Relative to classic clock tree synthesis, Nested Flex demonstrates 42.85% enhancement in latency and 32.30% skew reduction. When compared with Multi Source Clock Tree Synthesis (MSCTS), it exhibits 20.83% reduction in latency and 43.18% decrease in skew. Impressively, Nested Flex efficiently condenses a 23-level clock depth to a mere 15 levels, addressing the on-chip variation (OCV) dilemma and establishing a new benchmark for reliable clocking solutions. In terms of power metrics, Nested Flex yields a 15% improvement in total power and 15.82% enhancement in clock power over classic CTS. Additionally, when compared to MSCTS, it achieves 8.38% betterment in total power and 7.03% improvement in clock power.