Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting

Linearity testing, including differential nonlinearity (DNL) and integral nonlinearity (INL), is of great significance to evaluate the performance of an analog-to-digital converter (ADC). However, highly linear signal generator and large amount of samples are two challenges in conventional histogram testing method. This paper proposes a segmentation nonlinear model with partial polynomial fitting to reduce the required samples, while the source nonlinearity removal scheme relaxes the precision requirement of signal generator. The influence of noise and source resolution are analyzed. Measurement results show that with a 12-bit digital-to-analog converter (DAC) and 393 216 samples, the 16-bit ADC INL and DNL can be measured with estimation errors less than 0.3 LSB.