A Microwatt/Channel Neural Signal Processor for High-Channel-Count Spike Detection and Sorting

Next generation of brain-computer interface (BCI) aspires to achieve accurate and real-time spike sorting while being power--efficient. To achieve on-chip high-channel-count neural signal processing, accurate and hardware-efficient algorithms are critical. This work proposes a spike-sorting system that includes a NEO spike detector with an automatic threshold trainer, spike alignment and a feature extractor based on the first-and-second-derivative (FSDE) algorithm. The system employs a time-interleaving structure to reuse the logic cells, thus reducing the area and leakage power. The proposed system is implemented in ASIC in both 65 nm and 180 nm CMOS technologies with different folding ratios, and the product of power and area is optimized when a DSP core interleaves 8 channels. The implemented design in a 65-nm technology occupies 2.69 × 10
^-3
mm
²
/channel and consumes 0.52μW/channel at a 1.2-V supply. The accuracy simulations show that the proposed NEO (δ= 1) and FSDE algorithms achieve the average spike-detection accuracy of 97.1% and clustering accuracy of 91.6%, respectively.