Digital Background Calibration Techniques for Interstage Gain Error and Nonlinearity in Pipelined ADCs

This paper proposes a novel digital background calibration technique for interstage gain error (IGE) and gain nonlinearity in pipelined analog-to-digital converters (ADCs). Through the random switching of the multiplying digital-to-analog converter (MDAC) between two operating modes, two interstage residue curves are obtained. The IGE and the third-order gain nonlinearity are calibrated according to the distance and the geometric relationship between the two residue curves, respectively. For the proposed calibration scheme, the analog circuits require no modifications, except for the addition of several multiplexers and switches. The advantages of the proposed technique include a simple algorithm, fast convergence, and low power consumption. The simulation results show that the signal-to-noise and distortion ratio and spurious-free dynamic range of a 14-bit 1 Gsps pipelined ADC improve from 44.86 and 55.54 dB to 77.99 and 86.16 dB, respectively, after calibration. During the calibration process, the IGE and gain nonlinearity converge after 2.5 × 10⁵ and 2 × 10⁵ sampling cycles, respectively.