An SRAM Compute-In-Memory Macro Based on Direct Coupling SAR ADC and DAC Reuse

Deep neural networks (DNNs) can be implemented in low-power, small-area systems using compute-in-memory (CIM). This study proposes a CIM MAC macro based on 8T SRAM and a 5-bit Successive Analog-to-Digital Data Converter (SAR ADC) readout circuit to execute low-power and highspeed calculations. This architecture has no buffers between the low-power SAR ADC and the pre-stage. The SAR ADC’s capacitors are reused throughout calculating operations. The proposed macro is implemented using 55nm technology and achieves an INT4 throughput of 23.27 GOPS per ADC and an energy efficiency of 49.85 TOPS/W with 4-bit input, 4-bit weight, and 5-bit output.