PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks

The in-memory computation technique has a strong potential to improve the speed and energy efficiency of data-intensive tasks used in Artificial intelligence (AI). In this work, a time domain-based in-memory computation (TD-IMC) architecture is proposed to perform XNOR-and-accumulation (XAC) operations using two types of delay cells. The first XNOR and delay cell (XDC) is the base cell, which contains an XNOR gate and a stack-inverter-based delay cell to perform XNOR- and-accumulation (XAC) operations. The second process-voltagetemperature (PVT)-insensitive XNOR-and-delay cell (PXDC) is a PVT-tolerant cell, which contains the base cell and an array of controllable load capacitors to compensate for PVT variation. To demonstrate the application of the proposed TD-IMC XAC operation, the MNIST image classification is performed using a binary neural network (BNN) algorithm. The post-layout simulation results of the proposed architecture in an industrial 65 nm CMOS process show a classification accuracy of 99.6% compared to the software results. Moreover, the proposed TD-IMC achieves 1057/3.01 GOPS and 673/13.12 TOPS/W energy efficiency for XDC/PXDC-based TD-IMC architectures, which are comparable to the state-of-the-art TD-IMC architectures available in the literature.