A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections

In this work, we present a fully parallel reconfigurable spiking neural network (SNN) accelerator for various applications of edge computing. In contrast to conventional fully connected and irregular sparse network topologies, structured sparse synaptic connections are introduced to implement SNN in fully parallel on hardware by significantly reducing neuron computation and weight memory costs. Benefiting from the hardware-friendly symmetric SNN topology, the proposed accelerator is flexibly configured into multiple classifiers without hardware redundancy to support various tasks. Furthermore, to compress the layer depth of individual classifiers to reduce latency, layer-skip connections are introduced to alleviate the vanishing gradient problem in training. Various experiments are conducted to explore the optimal settings of the proposed accelerator. The proposed SNN accelerator is verified on the Xilinx ZCU102 FPGA. The results show that the proposed SNN accelerator achieves accuracy of 97.1% and energy efficiency of 40.1 GSOP/s/W on the MNIST dataset.