A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.