A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement

This paper describes a Fractional-N Phase Locked Loop (PLL) for multi-phase (=M) clock generation by reducing capacitor area. The M-phase clocks from the Voltage Controlled Ring Oscillator (VCO) have a frequency between N and N+1 times of a reference clock by second-order Delta Sigma Modulator (DSM). The reference clock is divided into M-phase clocks by Delay Locked Loop (DLL). The DSM assigns N or N+1 to a programmable divider (DIV), and the M DIV and DSM are prepared to feed M-phase divided VCO clocks. The divided VCO clocks and the reference clocks are compared respectively during one cycle of the input clock. This PLL system is equivalent to multiplying the input clock frequency by M, and the loop bandwidth of the PLL can be wider (×M) by reducing the capacitance value to one-Mth (÷M) in a loop filter (LF). To achieve the system, i) the divided VCO clocks should be generated by adding appropriate delay, and ii) the threshold value of each DSM has to be set properly. Measurement results of a test chip show equivalent frequency fluctuation and phase jitter of VCO clocks between conventional PLL with capacitance value C and the proposed PLL with capacitance value C÷M.