A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS

This work proposes a 2
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-1, low power, half-rate, StrongArm latch based pseudo-random bit sequence (SAL-PRBS) generator at a 15-Gb/s data rate. The proposed SAL-PRBS consumes low static-power consumption compared to current-mode logic (CML) based PRBS circuit topologies, thanks to the StrongArm latch (SAL) comparator circuit topology having virtually zero static power consumption. The proposed design is implemented in 1.2 V, 65 nm CMOS. The simulation results show that the SAL-PRBS consumes only 3.7 mW at a 15-Gb/s data rate. The output data sequence of SAL-PRBS has rail-to-rail output voltage signal swing with a timing jitter of 2 ps. The figure-of-merit(FoM) of the proposed SAL-PRBS generator is only 0.036-pJ/bit at a 15-Gb/s data rate.