An FPGA Implementation of An Event-Driven Unsupervised Feature Extraction Algorithm for Pattern Recognition

This paper presents the Field Programmable Gate Array (FPGA) implementation of an event-driven unsupervised Feature Extraction using Adaptive Selection Thresholds (FEAST) algorithm for pattern recognition tasks. The novelty of the design lies in splitting the FEAST learning rule into two different sets of tasks and executing them independently in a time-multiplexed fashion, using a minimum number of hardware resources. The proposed hardware architecture, operated at 200 MHz clock frequency, can process 183 × 10
³
events/sec in training mode and 196×10
³
events/sec in inference mode. The FEAST hardware model was tested with the Poker DVS dataset, obtaining a test accuracy of 95%.