Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE)

This paper presents the approach to design the inverter based CTLE at the minimum power consumption point and at minimum noise power product point while meeting the desired specification target. Lagrangian function for constrained optimization is formed. Mathematical close form expressions of the CTLE parameters are derived. Using the proposed design approach, an inverter based CTLE architecture with four different design constraints was designed and simulated in 16nm FinFET and in 65nm CMOS technology to validate existence of minimum power point design.