SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin

This manuscript proposes an SRAM-based hybrid analog compute-in-memory (CIM) architecture to enhance the signal margin. This hybrid architecture presents fully differential current-based and C-2C charge-sharing-based multiplication and accumulation (MAC) CIM schemes for 4-bit MAC operation. The MAC operation of the filter weight's least significant bits (w
0
and w
1
) is implemented in the current-based CIM. However, the MAC operation of the most significant bits (w
2
and w
3
) is implemented in the charge-based CIM. The proposed architecture achieves a 4.37× enhancement in signal margin compared to the state-of-the-art. The energy efficiency and throughput of the proposed architecture are 1551.5 TOPS/W and 512 GOPS, respectively, at 0.9 V supply voltage and 250 MHz frequency. A convolutional neural network (CNN) is implemented on the proposed architecture, and the inference accuracy for the MNIST and CIFAR-10 data sets is 98.6 % and 86 %, respectively. The proposed architecture is scalable for multi-bit MAC operation and implemented in 28 nm CMOS technology.