A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI

This work presents an ultra-low-power, single-ended successive approximation register (SAR) analog-to-digital converter (ADC) designed explicitly to digitize sensor data. Due to the single-ended nature of the sensor’s output data, very efficient designs for differential SAR ADCs cannot be utilized. Hence, a monotonic capacitor switching procedure for single-ended inputs has been developed and is introduced in this paper. Re-charging of capacitances during the SAR algorithm is no longer required, resulting in significant energy savings compared to conventional approaches.The SAR ADC is implemented in a 22nm CMOS FDSOI technology. It achieves a measured signal-to-noise and distortion ratio (SNDR) of 49.1dB and a spurious-free-dynamic-range (SFDR) of 61dB. It draws a simulated 1.2μW yielding a Walden figure of merit (FoM
W
) of 50.2fJ/conversion step at a sampling rate of 100kS/s. The circuit occupies an area excluding pads of only 275 x 220μm
²
.