Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator

Compute-in-memory-based accelerators have gained significant attention due to their promising potential. However, many studies in this area often focus solely on the accelerator's performance without considering the latency and energy consumption associated with external data access. Moreover, many have observed a gap in energy efficiency between the macro and the accelerator levels. Our work addresses this problem by proposing an SRAM CIM-based AI accelerator design that reduces additional memory access and mitigates the overhead associated with external data access. Our results demonstrate that lowering the ratio of total local memory capacity to total CIM macro capacity closes the energy efficiency gap between the macro level and the accelerator level.