Research Experiences for Teachers on Chip Design

This paper presents the first Research Experience for Teachers (RET) site in the United States on integrated circuit (IC) design and education for high school and community college teachers. Motivated by the enormous upcoming semiconductor workforce demand spurred by investments from the CHIPS and Science Act, we offered a six-week paid RET program for ten teachers in Oklahoma to learn about semiconductors and chip design. Teachers were also required to translate their experience into new curriculum modules. Our training leveraged the web-based Silicon Layout Wizard (Siliwiz), Wowki template, and the Tiny Tapeout flow, all running in a browser using the open-source Skywater 130 nm CMOS process. We also provided curriculum design training so teachers could teach the new materials more effectively. Among the ten participants, six successfully submitted their GDS files for fabrication. Four presented at the 2023 ASEE virtual poster sessions. Evaluation data indicated the challenges teachers initially faced and the enthusiasm they sustained throughout the RET program.