Analysis and Design of Constant-Slope Voltage-to-Time Converters

Time-based analog-to-digital converters (ADCs) have recently gained attention because of their ability to reach high sample rates with good energy efficiency. The performance of most implementations is limited by the Voltage-to-Time Converter (VTC), hence necessitating thorough analysis on its performance. This paper derives expressions for the noise and linearity of a constant-slope VTC. The derived expressions provide an explicit link between the circuit parameters and VTC performance as well as offer insight on the available trade-offs. Based on the expressions, a general design methodology for constant-slope VTCs is proposed. The simulated verification with 28-nm CMOS shows good agreement with the presented analysis and with previously measured results, thereby corroborating the proposed design methodology. The presented design methodology allows the developed understanding between the VTC circuit parameters and performance metrics to be utilized in e.g. design exploration and algorithmic circuit optimization to find an optimal set of parameters for a given target specification.