A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases

Cardio-vascular diseases (CVDs) are growing rapidly these days, which motivates to design an ultra-low power wearable cardiac monitor for early detection. In this work, we proposed an ultra-low power application-specific integrated circuit (ASIC) that can detect the P, R, and T peaks of the Electrocardiogram (ECG) signal. These peaks are useful for early detection of CVDs. The proposed design consists of a low-power analog front end followed by a peak-detection circuit, which can detect the P, R, and T peaks from an incoming single-lead differential ECG signal. The time-varying amplitude difference between the adjacent ECG peaks are efficiently detected by the proposed design. The proposed peak detector circuit has a self-adjustable discharge rate, which depends on the amplitude of the peak. The circuit is designed at the sub-threshold region to reduce the power consumption of the overall design. The proposed design extracts the digital output with the temporal information from the peaks of the ECG signal without using an analog-to-digital converter (ADC), one of the most power-hungry blocks in conventional biomedical signal acquisition architectures. A test chip has been fabricated in an industrial 0.18 µm CMOS process and occupies an active area of only 0.848 mm
²
. Measured results show that the proposed design consumes only 299.45 nW of power with a supply voltage of 0.9 V at typical operating conditions, which represents an improvement of 27.07%, 34.57%, and 51.93% over the existing state-of-the-art design. As it consumes ultra-low power, occupies less silicon area, and reliably extracts the ECG peaks, the proposed design is highly suitable for wearable healthcare applications.