Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory

Resistive Random Access Memory (RRAM) is a promising low-power memory candidate because of a large R-ratio (R
HRS
/R
LRS
). Multi-level RRAM cells have been investigated to improve memory density and cost-per-bit. However, sensing multi-level becomes challenging due to the smaller R-ratios between stored digital values. This paper introduces a novel time-based sensing (TBS) scheme for enhancing the robustness and speed of the read operation, supporting from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the current-to-time converter (CTC) converts the bit line (BL) current into a time delay based on the cell states. Different time delays from HRS and LRS values are compared to generate digital data. Unlike conventional current-based sense amplifiers (CSA) or voltage-based sense amplifiers (VSA), the proposed sensing scheme does not require a reference array or generator. Comprehensive simulation in 40nm CMOS technology shows enhanced linearity and higher read speed because of the precise replication of cell current to CTC. As a result, the proposed TBS achieves a sensing latency of < 2ns with an energy consumption of 61fJ/bit for read operations at 1.1 V and also supports MLC sensing through a single read operation.