A Tri-loop Fast-transient Digital LDO with Adaptive-gain Control and Fine-loop Freezer

In this paper, a fully-integrated digital low dropout (DLDO) regulator is proposed utilizing a multi-bits shift handler (MBSH), decremental-gain PMOS array, and adaptive coarse loop controller to achieve fast load transient responses with improved line and load regulations. An undershoot-limiter loop (ULL) is also proposed to help to reduce the voltage undershoot peak during load current transients. To significantly mitigate the steady-state voltage ripples (V
RIPP
) and quiescent current (I
Q
), we propose a synchronized fine-loop freezer (FLF) in the fine loop of the DLDO that is only activated when V
REG
gets equal to V
REF
. The proposed DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.22 mm
²
. The simulation results demonstrate that the proposed DLDO achieves ≤ 130 μV of V
RIPP
while maintaining a minimum dropout voltage of 20 mV and a peak current efficiency of 99.96 %.