Toward Accurate Analysis of Channel Charge Injection in SAR ADCs' Capacitive DACs

This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effective compensation methods rather than relying on simple dummy switches by detecting most effective switches. All simulations are conducted using Cadence TSMC 130nm CMOS technology and MATLAB software, implying on 5 to 7 dB degradation in SNDR when considering the effect of channel charge injection in 6, 9, and 12-bit typical SAR ADCs.