A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator

This paper presents the architecture and implementation of a low-noise sub-sampling phase-locked loop (SSPLL) for mm-wave frequencies. It leverages an LC oscillator with a novel resonator, a digital lock assist and frequency calibration system as well as a novel charge pump implementation. The charge pump eliminates the pulser and runs continuously, which significantly reduces its power consumption while maintaining equal noise performance. The calibration system solves the lock problem of the SSPLL by implementing a lock/frequency search to prevent non- and false-lock. The LC oscillator employs an optimized resonator which combines both the inductor and the capacitor on the same metal, resulting in a very high quality factor by eliminating the interconnect resistance within the resonator. The SSPLL was implemented and simulated in a 22-nm-FDSOI technology, alongside with measurement results of the LC oscillator, which was fabricated in the same technology.