A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction

This paper presents a period jitter measurement circuit that employs a stochastic phase interpolation scheme. Triggered by an input clock, a delay line is applied to sample the signal under measurement. By appropriately delaying the input clock by less than one cycle and utilizing the rising edges of the delayed clock and input clock, the circuit generates a signal for measurement, minimizing the usage of delay units and enabling the measurement of a period greater than the average. A two-mode measurement scheme is adopted. In calibration mode, the phase difference between the input and delayed clock is measured for calculating the average clock period. Accurate period jitter is measured in normal mode. An averaging strategy is employed to mitigate the offset introduced in the signal generation. The proposed circuit is implemented on a Kintex Ultrascale+ FPGA, achieving a difference of 0.8 ps compared to the reference root mean square value with resource consumption of 7712 FFs, 1098 CARRY8s, and 8629 LUTs.