A Wide-Range Reference-Less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition

This paper presents a digital clock and data recovery (CDR) designed for a faster approach to its steady-state and prevention of harmonic locking. By adopting a two-stage frequency detection system, the proposed CDR ensures a rapid and robust harmonic-lock-free frequency acquisition. The circuit is implemented and fabricated in a 28 nm CMOS process using a 1.0 V supply. The active area occupies 0.12 mm
²
. It covers from 1.62 to 8.1 Gb/s, making it adaptable to embedded DisplayPort (eDP) interfaces. The prototype achieves the rms jitter and the peak-to-peak jitter is 5.54 ps
rms
and 27.53 ps
pp
at 8.1 Gb/s, respectively. Its lock time is reduced within 2 μs for +170% frequency error.