SAR-MemPipe: A Hybrid Pipeline-SAR Memristive ADC for Analog Resistive Arrays

This paper presents a hybrid pipeline SAR ADC with a loop-unrolled structure to reduce the crossbar’s ADC power while maintaining high speed. The 1
^st
stage memristive SAR ADC can fully utilize the TIA originally in the crossbar and avoid the extra MDAC in pipeline ADC. Further, memristive weight calibration and a new resistive alternated binary search are implemented on the 1
^st
stage to maintain the TIA gain and ADC’s accuracy. Both stage’s ADC are loop-unroll to eliminate the delay brought by SAR logic for high speed. Through multiple simulations, the design is demonstrated to be robust to the frequency and mismatch variations with the highest sampling frequency reaching 300MHz and SNDR up to 65.1dB in 9MHz input. The power consumption is designed to be as low as 6.7mW, which helps the ADC to achieve a 15.2fJ/conv FoM. Not limited to the crossbar, the presented ADC also shows promising potential for applications in various fields (biomedical, IoT etc.) for general purposes.