A 91 dB SNDR Calibration-Free Fully-Passive Noise-Shaping SAR ADC with Mismatch Error Shaping

This paper presents an energy-efficient calibration-free hybrid noise-shaping SAR ADC for low-power high-resolution applications. A high-efficiency 2nd-order fully- passive noise-shaping technique is adopted in this circuit to achieve higher in-band noise attenuation for a better signal-to-noise ratio (SNR). Mismatch error shaping with digital prediction is used to mitigate harmonic distortions without affecting ADC's dynamic range, therefore greatly improving the signal-to-noise-and-distortion ratio (SNDR) and spurious- free dynamic range (SFDR). The prototype ADC is designed in 55 nm CMOS and occupies an area of 0.126 mm
²
. It consumes 7.426 μW at 400 kS/s sampling rate from a 1 V supply. The post-layout simulated SNDR is 91.05 dB for a 6.25 kHz bandwidth without any calibration, resulting in a Schreier figure of merit (FoMS) of 180.30 dB and a Walden figure of merit (FoMW) of 20.40 fJ/conversion-step.