Analysis of Random Clock Jitter Effect in Time-Interleaved DACs

This article aims at providing intuitive and quantitative insights into the impacts of random clock jitter on the signal-to-noise ratio (SNR) of the time-interleaved (TI) digital-to-analog converters (DACs) (TI-DACs). A novel method is proposed to thoroughly analyze the impact of jitter in the frequency domain for TI-DACs. Closed-form equations of the DAC SNR are derived for both correlated jitter and uncorrelated jitter, with and without misalignment between sub-DACs’ clock edges. A behavioral model is built in MATLAB and simulations are carried out to validate the analysis.