Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory

Computing-in-memory (CIM) based on spin transfer torque magnetic random access memory (STT-MRAM) is promised to be an effective way to overcome the "memory wall" bottleneck. In this work, we proposed a novel complementary series-connected magnetic tunnel junction (STT-MTJ) structure for time-based Computing-in-Memory (CST-CIM). The bit-cell with four transistors and one MTJ is utilized to establish a series-connected structure to improve the limited resistance of MTJ, which can be applied for high-linearity and sufficient-margin multiply-and-accumulate (MAC) operation. In addition, for peripheral computing circuit, a customized successive-approximation-register time-to-digital converter (SAR-TDC) is used for high energy efficiency and low latency. To optimize the multi-bit MAC operation, we proposed a novel hardware friendly signed binary weight mapping strategy, which can provide the computing flexibility with 1-8bit quantization. Simulation result shows the proposed CST-CIM architecture can achieve low computation latency of 5ns and peak energy efficiency of 106.7 TOPS/W.